Integration of III-V materials, such as gallium nitride, onto (100) silicon surfaces (100) is highly desired for such applications as) high voltage and RF devices for System on chip (SoC) technology, as well as for complementary metal oxide silicon (CMOS) applications. This integration involves fabrication challenges that may arise due to the mismatch in lattice properties between the two materials. This lattice mismatch, which may be near forty two percent, may cause epitaxial growth of low defect density III-V materials to become prohibitive. Additionally, the large thermal mismatch between gallium nitride and silicon (which is about one hundred and sixteen percent) coupled with conventional high growth temperatures for gallium nitride, can result in the formation of surface cracks on epitaxial layers, thus inhibiting the use of III-V materials on Si (100) for device fabrication.